Unexpected WDT Behavior

Discussions around product based on ARM Cortex M0+ core.

Moderator: nferre

Posts: 9
Joined: Tue Jun 18, 2013 9:47 pm

Unexpected WDT Behavior

Thu May 08, 2014 7:37 pm

I am using the following code to configure my WDT:

Code: Select all

void watchdogSetup(void) {
	//Do not need to configure generic clock --> enabled by default
	//Using clkgen 2, sourced from OSCULP32K
	//This is redundant -- peripheral clock is enabled by default after reset
	//Ensure WDT is disabled (configuration is enable-protected)
	WDT->CTRL.reg = 0x00;
	//Set time-out period (not using window functionality)
	WDT->CONFIG.reg = WDT_CONFIG_PER(WDT_DELAY_16384_CYCLES);	//16384*(1/32768) = 500ms
	//Ensure early warning interrupt is disabled
	//Enable WDT
	//Set always on bit to prevent accidental disablement
//	WDT->CTRL.reg |= WDT_CTRL_ALWAYSON;						//leave this commented out while testing code (w/ frequent d/ls) --> can only be reset by power cycle
I am testing it on a SAMD20J18 Xplained board (i.e., programming the chip via the EDBG on the Xplained board). I am using the GUI programming interface in Atmel Studio 6.1, programing the Flash, with the options "Erase Flash before programming" and "Verify Flash after programming" selected.

In my main code, I have the capability to bypass the routine that kicks the WDT -- as a test. If I program the board, and allow it to start executing without power cylcing (i.e., it recovers from a SYST reset at the end of the programming cycle), the WDT does not seem to work. Meaning, I trigger the code to stop kicking the WDT, and it never resets. However, if I issue an external reset (strobe the reset pin) or power cycle the board, the WDT works exactly as expected.

I suspect that this has something to do with how/when the chip reads the NVM User Row. In the SAMD20J18 data sheet, under the WDT section, each register says that the "bits are loaded from NVM User Row at startup."

Does this mean that when I set the bit in WDT->CTRL to enable the WDT, it doesn't really enable the WDT -- it only sets the bit in the NVM User Row, so that at next power up/reset (except for SYST resets), the WDT will be enabled?

Edit: this is what Table 15-2 (p. 107) and Figure 15-3 (p. 108) seem to show -- if I am interpreting them correctly -- except for the fact that hitting the reset pin on the Xplained board seems to force the WDT registers to re-update from the NVM.

Return to “SAM D20 Cortex-M0+ MCU”

Who is online

Users browsing this forum: No registered users and 1 guest