Generic question regarding atomicity of access

Discussions around product based on ARM Cortex M0+ core.

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hobbss
Posts: 9
Joined: Tue Jun 18, 2013 9:47 pm

Generic question regarding atomicity of access

Fri Apr 25, 2014 9:50 pm

On an [8-bit] AVR, if I share a "large" variable -- anything bigger than 8 bits (i.e. uint16_t, uint32_t, float, etc) between "normal" code and an ISR, in addition to making it volatile, I would use the macros from util/atomic.h (http://www.nongnu.org/avr-libc/user-man ... tomic.html) to guarantee that accesses were not interrupted.

On a 32 bit processor like the SAMD20, is that necessary, or are all accesses (except double precision and 64 bit variables?) by definition atomic, since they can be done in a single clock cycle?
jharley
Posts: 238
Joined: Thu Dec 06, 2012 6:40 am

Re: Generic question regarding atomicity of access

Sat Apr 26, 2014 9:57 pm

Depends on your alignment.

From the "ARMv6-M Architecture Reference Manual" which covers the Cortex-M0+ MCU
The only ARMv6-M explicit ARM processor accesses that exhibit single-copy atomicity are:
• all byte transactions
• all halfword transactions to 16-bit aligned locations
• all word transactions to 32-bit aligned locations.
hobbss
Posts: 9
Joined: Tue Jun 18, 2013 9:47 pm

Re: Generic question regarding atomicity of access

Wed Apr 30, 2014 10:40 pm

Thank you for the response.

At your suggestion, I have referenced the ARMv6-M Architecture Reference Manual (specifically pp. 49-50). However, I am still unsure how to determine if my memory/register access meets the requirements to be atomic (i.e., "all word transactions to 32-bit aligned locations").

Where can I learn how variables are actually aligned? I have looked through the gcc documentation and the SAMD20J18 data sheet without a lot of luck.

I apologize in advance if this question is dumb...
pozz
Posts: 67
Joined: Fri Jun 13, 2014 2:55 pm

Re: Generic question regarding atomicity of access

Wed Jun 18, 2014 9:12 am

I'm interested on this too.

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